[Uniquify] Tuyển Senior Physical Design và DFT Engineer Tháng 07/2018

Uniquify Viet Nam One Member LLC
Level 7, Thien Son building, 5 Nguyen Gia Thieu street, ward 6, district 3, HCMC
Level 5, Indochina Riverside Tower building, 74 Bach Dang street, Hai Chau 1 ward, Hai Chau district,
Da Nang city
Work Location: Ho Chi Minh, Da Nang

- Following standard practices, implement and verify deep sub-micron multi-million gate SoC (System on Chip) ASIC Designs;
- Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, development, design and implementation of top/block level floor-plans;
- Performance of clock-tree synthesis and high fan-out net synthesis;
- Plan place and route architecture; conduct static timing analysis. Implement DRC, LVS and Antenna;
- Determine the cause of any potential cause for gate array failure, ensuring parasitic extraction; and, perform design validation and provide formal verification.

1. Senior Physical Design Engineer:
- Bachelors or Master’s degree in Engineering with 3+ years of ASIC physical design ( place and route ) experience;
- Proven APR hands-on tapeout ASIC experiences in 45nm and/or below technologies, fluent with Netlist-to-GDS flow using Sysopsys/Cadence tools;
- Experienced to be an APR block owner or top-level integration/floorplanning/ APR engineer;
- Must be able to work independently, to collaborate with different teams, and to be flexible to take dynamic and challenging assignments. Must have good communication skills, and can take tapeout pressure;
- Experienced in Tcl/Perl scripting to innovate APR methodology;
- Low power implementation;
- Familiar with synthesis (RTL to Netlist);
- Experience in digital design flows including RTL synthesis, STA, PNR and Physical Verification. Experience with Cadence, Synopsys tools a plus;
- Preferred if you have managed a team of Physical Design Engineers;
- Strong understanding of LINUX & windows operating systems;
- Programming experience with tcl, Perl, and Shell;
- Strong written and verbal communication skills.
2. Senior DFT Engineer:
- 3+ years of DFT experience, leading DFT efforts for SOC designs;
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time;
- Experience developing DFT specifications and driving DFT architecture and methods for designs a plus;
- Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools;
- Knowledge of industry standards DFT and design tools;
- Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues a plus;
- Experience with STA constraints development and analysis for DFT modes and SDF simulations a plus.



Mr. An Huynh, This email address is being protected from spambots. You need JavaScript enabled to view it.