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[Synopsys] Analog IC Design Job
[Synopsys] Analog IC Design Job

Synopsys is opening internship students who are finding opportunity in this summer.

Now if you would like to contribute to our Smart Everything Era, Let's join us!
Intern positions ( 8 Interns)

Analog Circuit/ Layout Intern (JD & Requirements): http://bit.ly/intern-ams-hcm

Joining our

UIT CAR RACING 2021 - Ready for the race
UIT CAR RACING 2021 - Ready for the race

The UIT CAR RACING 2021 race track has officially opened the registration portal for genuine "DIGITAL CAR" enthusiasts. UIT CAR RACING in 2021 includes 2 models:
Open session: for new racers who are high school students and students of the first and second years of schools in Ho Chi Minh City.

Everything You Need to Know About Smart Home Networking
Everything You Need to Know About Smart Home Networking

Learn the difference between Wi-Fi, Bluetooth, Zigbee and Z-Wave

Right now, as you kick back on your couch and daydream about your next smart home upgrade, you may not realize it, but you’re awash in data. From Wi-Fi-enabled thermostats to Bluetooth-accessible door locks to Z-Wave-connected alarm

Design Virtualization Technology: VMWare for SoCs

by Paul McLellan

It was way back in 2001 that Pat Gelsinger, then CTO of Intel, pointed out that if we kept increasing clock rates that chips would have the power density of rocket nozzles and nuclear reactor cores. Ever since then power has been public enemy #1 in chip design. In 2007 Apple announced the iPhone and the application processor inside it, and smartphones became one of the most intense battlegrounds for power. After all, the length of time that a battery lasts is much more visible to the consumer than, say, the power dissipated by the chips in their wireless router. But routers are not immune to power either, at least at the datacenter level.

There is a sense in which all chips today are low power. A chip for a hearing aid might have power measured in millwatts whereas a chip for a datacenter might have a budget of 150W. But both chips are face the challenge of meeting their performance, very different of course, under their power envelope.

There are many techniques for power reduction, way beyond the scope of a single blog. But some of the most confusing are the selection of libraries, process technology, signoff corners, giving up yield for power, multiple voltage rails and so on. Basically, what underlying fabric should be used to construct the design.

eSilicon have a huge amount of data on this sort of thing based on the large number of designs they have run and also on a lot of additional characterization that they have done in addition so that they can easily estimate the effect of, say, reducing the upper temperature for characterization to 100°C (nobody's cellphone can run that hot or your pockets catch fire) or lower bound to 0°C (when did you last see a datacenter with icicles), or lowering the margin of error on the voltage regulator from 5% to 3%. They call this design virtualization technology. Today this is provided as a service but under the hood is a lot of software and a huge amount of characterization data of all types, far more than is practical to process by hand or even in Excel.

Rather than give the marketing pitch, I think it is good to actually show a real-world example of the technology in action on a real design. eSilicon worked with a customer on a design to go into a networking design. When the design was essentially complete the first power estimate came up at 130W. which was too much for the power budget of 75W.

Design virtualization technology to the rescue:

  1. Where is the power coming from? 95% of the power turned out to be coming from a single 450MB memory.
  2. Can we customize the memory? Yes. So eSilicon did that using an off-the-shelf memory from their extensive portfolio of memory IP that they develop internally. They then removed all the peripheral logic that supports options not required for this particular design. There were also device swaps in the periphery by using libraries with multiple thresholds.
  3. This got the power down to 90W, but the customer target was lower at 75W. eSilicon’s design virtualization technology analyzed the design. By applying low power techniques such as lowering the core voltage a tiny bit, using more multi-Vt libraries and so on they achieved 75W. The chip was 3 days away from its scheduled tape-out. But at this stage life looked good.
  4. Marketing came back and said the power budget had to be 35W. eSilicon fired up their design virtualization technology again. If they got aggressive at voltage, temperature and process corners could they get there? What about frequency? Was there any flexibility to reduce that and still meet the performance requirements?
  5. It turned out they needed to do all 4. Voltage down 2%. Tighter process window, eating a tiny potential yield loss, temperature maximum of 105°C, Frequency from 500MHz down to 400MHz. Power at 35W.
  6. Tapeout on schedule 3 days later. Success.

One thing that I learned covering from this design is that 3 sigma really is very conservative. If you reduce that to 2 sigma then the maximum yield loss is under 5% but the potential gains in power (and performance) can be significant. But you need a lot of data to make that kind of change with confidence, and design virtualization technology is your "ring of confidence."

The eSlicon White Paper on power reduction using design virtualization technology is here.


From: https://www.semiwiki.com/forum/content/4614-design-virtualization-technology-vmware-socs.html